A. Field of the Invention
The present invention relates to a method for manufacturing a silicon carbide (hereinafter referred to as SiC) semiconductor device for a high breakdown voltage and large current, especially to a method for manufacturing a SiC semiconductor device having a trench gate structure.
B. Description of the Related Art
A power MOSFET and an insulated gate bipolar transistor (hereinafter referred to as IGBT) are well-known and widely used as silicon (hereinafter referred to as Si) power semiconductor devices for an inverter and an AC power control. However, it has been widely observed that a material of Si as a semiconductor material has already neared its physical property limit in respect to semiconductor characteristics in the power semiconductor device. Thus, a SiC semiconductor, which has a physical property limit higher than that of the Si semiconductor, has received attention. As compared with Si semiconductor material, SiC (especially its crystal form of 4H-SiC) semiconductor material has excellent features in dielectric breakdown electric field, band gap, thermal conductivity and temperature of an intrinsic semiconductor, with these properties of the SiC semiconductor material being respectively higher in one digit, in 2.9 times, in 3.2 times and in 3 to 4 times than those of the Si semiconductor material. Therefore, superior performance of the SiC semiconductor material is greatly shown its better physical property limits in comparison with the Si semiconductor material in the case of using the SiC semiconductor material as a substrate material, especially for a power device. As a result, in a power device using a SiC semiconductor substrate, a high breakdown voltage characteristic and a low on-resistance characteristic can be simultaneously achieved in spite of an assumption that it is difficult to achieve these characteristics at the same time, there being a trade off relationship between them in the Si semiconductor device, and there have been many approaches to the manufacturing in recent years. However, there are still a lot of problems which are not solved for an actual manufacturing process to manufacture or practically use this as a power device.
On the other hand, in recent years a trench gate structure has been used as one of high density patterning techniques that has been developed to reduce on-resistance or an on-state voltage of the power MOSFET and the IGBT using the Si semiconductor. FIG. 7 shows a cross-sectional view of a unit part of the MOSFET having the trench gate structure. The trench MOSFET is a device including as main elements n-type high resistance layer 102 formed on a principle surface of n-type substrate 101, p well layer 103, n emitter region 104 formed in a surface layer of p well layer 103, trench 105 formed by etching to a depth reaching n type high resistance layer 102 from a surface of n emitter region 104, gate oxide film 106 formed on a surface of trench 105, and gate electrode 107 of conductive polycrystalline silicon (polysilicon) buried in trench 105 interposing gate oxide film 106 between trench 105 and gate electrode 107. An etch process must precisely form width, a depth and a flat surface of trench 105 to produce the semiconductor characteristics in manufacturing, and thus the etch process is very important. In addition, because a required depth of trench 105 is different in response to the breakdown voltages, it is necessary for trench 105 to have at least several micrometers of depth at several hundred volts in the breakdown voltage. When a high breakdown voltage device is manufactured, an etching technique to enable formation of the required deep trench 105 and the etch process technique to control to make the preferred flat surface of trench 105 already have been approximately established in the Si semiconductor substrate.
However, because the SiC semiconductor substrate material according to the present invention is one of materials which is so difficult to etch that even practical wet etching has yet to be discovered, an etching control technology is not established enough in comparison with the above-described Si semiconductor substrate. It is disclosed in Japanese Patent Nos. 2992596, 2661390, 3593195 and 3761546 and Japanese Patent Laid-open (Publication) No. 8-12286 (hereinafter respectively referred to as Documents 1, 2, 3, 4 and 5, respectively) that it is possible to etch the SiC semiconductor substrate by dry etching such as reactive ion etching (hereinafter referred to as RIE) for the present. Document 2 (Japanese Patent No. 2661390) corresponds to U.S. Pat. No. 5,234,537 and European Patent No. 504912B1, and Document 5 (Japanese Patent Laid-open (Publication) No. 8-12286) corresponds to WO 02/099870 A1. However, because the etch rate of SiC semiconductor substrate is low in the RIE dry etching technology (the etching rate with the use of a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2) is around 50 nm/minute), and etching selectivity of the SiC semiconductor substrate to the material of a mask is also small, it is difficult to form a trench needing selective etching with the use of a mask, especially the deep trench. For example, it is difficult to etch a trench even to a depth of several micrometers.
On the other hand, it is known that dry etching with the use of high density plasma by an inductively coupled plasma (hereinafter referred to as ICP) method has an effective etching rate, but it still takes a long time to form the above-described deep trench (of several micrometers). Using the ICP method with a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2), and using an aluminum (Al) film or a nickel film having etching selectivity as the mask, allows the etching rate to be more than 100 nm/minute. However, there is a problem that the etched surface becomes rough due to contamination by mask metal and a micro mask adheres on the etched surface.
If a silicon dioxide film (hereinafter referred to as SiO2) is used as the etching mask in the above-described ICP dry etching, the problem caused by the metal mask does not occur. But when the selectivity ratio of the SiC semiconductor substrate to the SiO2 is not high enough chemically and physically, the mask is etched away before the etching target depth to form the trench is reached in the SiC semiconductor substrate. Because the selectivity ratio of the SiC semiconductor substrate to the SiO2 is around 3 when the SiC semiconductor substrate is etched and SiO2 of 2 μm in thickness is used as the mask in the ICP dry etching presently used, the SiO2 as the mask disappears when the SiC semiconductor substrate is etched to a depth of around 6 μm, so that it is not possible to form a trench that is deeper than that. In addition, if the film thickness of the mask is made thicker than 2 μm, it causes new problems, because it takes a lot of times to form the SiO2 mask and further it is difficult to pattern with good accuracy for the thicker mask material. Therefore it cannot be simply concluded that the problems are easily resolved by increasing the thickness of the SiO2 mask. Thus, the practical level for the depth of the trench is around 3 μm in current ICP dry etching with respect to the SiC semiconductor substrate.
Japanese Patent Laid-Open No. 2005-56868 (hereinafter referred to as Document 6) discloses that on a bottom surface of a deep trench formed in SiC semiconductor substrate 110 by dry etching with the use of ICP high density plasma, microtrench (subtrench) 112 is formed in a convexo-concave shape having an acute angle on the bottom surface of trench 111 as shown in FIG. 8. Further when the MOS device including the trench gate structure having microtrench 112 on the bottom surface of trench 111 is operated, dielectric breakdown occurs due to electric field concentration on an acute angle part of microtrench 112, and there is a major problem because the designed breakdown voltage cannot be obtained. In addition, Document 6 (Japanese Patent Laid-Open No. 2005-56868) discloses that the trench is formed in the SiC semiconductor substrate by a first ICP dry etching with the use of a mixed gas of carbon tetrafluoride (CF4) and oxygen (O2) to use the aluminum (Al) film as the mask, and a microtrench on a surface of the bottom of the trench formed by a first dry etching is relaxed by a second ICP dry etching on the entire surface of the SiC semiconductor substrate after removing the aluminum (Al) film as the mask.
Thus, no method is disclosed in Documents 1 through 5 in which a deep trench is formed by using a mask and in which etching selectivity of the SiC semiconductor substrate to the mask is large. Practical utility is low since it takes too much time to form the deep trench in the SiC semiconductor substrate due to the small etching rate in the etching method in description of Documents 1 through 5. Further, in Documents 1 to 5, there is not even a suggestion to flatly etch the trench bottom without convexo-concave of the acute angle so that the breakdown voltage characteristic of the MOS semiconductor device having the trench gate structure has not a bad influence.
In addition, a depth of the trench is around 3 μm in Document 6, and it is not explained that micro etching is improved by the second ICP dry etching by extent that the breakdown voltage characteristic does not have the bad influence in the case that the trench is formed in depth of more than 3 μm. Moreover, because the metal mask of aluminum or nickel is used as the etching mask in description in Document 6, metal contamination on the surface in the trench is not avoided. It is desirable to avoid using a metal mask.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.